UMC's Singapore fab just moved silicon photonics from the lab into production. On July 14, the Taiwan-based foundry and chip designer SILITH Technology announced the first delivery of mass-produced 12-inch silicon photonics wafers, optical interconnect chips manufactured at full wafer scale and ready for deployment in AI data centers. The milestone landed quietly inside Q2 earnings that beat forecasts, but the real event is the one almost no one outside the foundry business is watching: a second supplier just validated that the supply chain for advanced optical I/O can scale beyond TSMC's confines.
UMC's Fab 12i in Singapore is running the imec iSiPP300 platform, which the company licensed in December 2025 from the Belgian research institute. The process node is not cutting-edge logic, it lives in the mature-node and specialty-fab territory where UMC makes its money. The wafers support SILITH's 1.6-terabit silicon photonics platform, a system capable of moving 1.6 trillion bits of data per second down a fiber. That throughput is not theoretical. SILITH has customers, and those customers need optical interconnect in volume, not in pilot runs. The shipment validates both the process maturity and the manufacturing scale, 12-inch wafers mean UMC can run these chips through the same foundry infrastructure it uses for mature-node logic, which means real throughput and real cost structure, not a specialty cleanroom tax.
The numbers confirm the shift. UMC's Q2 revenue hit $2.12 billion with gross margin expanding to 32.5% and factory utilization climbing to 85% from 79% a quarter earlier. Those utilization gains came from somewhere, and the silicon photonics ramp is part of the story. Specialty processes, analog, power, RF, and now optical, are the leverage point in a mature foundry's mix. TSMC dominates cutting-edge logic. But TSMC's photonics roadmap is oriented toward co-packaged optics bolted onto chiplets, not monolithic optical I/O at 12-inch scale. UMC just moved into a segment where TSMC is not yet executing at volume, and Samsung, the third major foundry player, is even further behind. The imec licensing deal gave UMC a ready-made process platform, no reinvention required. SILITH gave UMC a first customer with real demand. The combination landed three months before either TSMC or Samsung public announcement of comparable 12-inch SiPho capacity.
CEO Jason Wang confirmed that Intel 12nm design kits will reach customers by year-end, opening UMC to a new external foundry pipeline. Intel's own photonics strategy has stalled in public view, but Intel's design-kit release signals that the company wants UMC capacity available to its customers, a direct lever against TSMC's optical interconnect roadmap. That competitive dynamic matters because the customer base for optical I/O is not optional anymore. Every large AI cluster is hitting optical interconnect constraints at bandwidth, and monolithic 12-inch SiPho is the path to higher data rates per chiplet. SILITH's 1.6-terabit platform is the proof point. If SILITH can push 1.6 terabits per second down a fiber, and UMC can manufacture it at volume on 12-inch wafers, then any hyperscaler designing optical I/O architecture has a second source beyond TSMC. That changes the negotiating position on both sides.
Watch for three markers over the next eight quarters. First, SILITH's product adoption curve, if their optical interconnect reaches production in actual AI clusters by Q1 2027, the capability is real and other optical-I/O designers will line up at UMC. Second, whether Samsung or TSMC announces comparable 12-inch SiPho volume by end of 2026, if neither moves before year-end, UMC owns a genuine technology window. Third, whether Intel's design-kit release in Q4 2026 unlocks new customer names to UMC's external foundry business. The silicon photonics market is not large in absolute terms, but it sits at the convergence of AI infrastructure, optical networking, and foundry competitive position. UMC just became a player in all three.